Silica MCP server
io.github.simaanc/silica-eda·v0.5.0·13 starsRTL and FPGA tools: lint, simulate, formal, synthesize, place and route, program a board.
13 stars301 downloads/wk
Reviews
Write oneNobody has reviewed Silica yet.
If you have run it, two minutes of your experience saves the next person an afternoon.
Silica tools (18, 5 write)
write = sends, deletes, buys or postsRead from the package source without running it. The installed server may list more.
capture_serialCapture a board's UART output, optionally sending text first.
doctorReport silica's version and which EDA tools it can use, with a fix for each gap.
format_rtlAuto-format a SystemVerilog/Verilog file and return a unified diff.
get_constraintsRead and return the content of a constraint file (.xdc / .sdc / .lpf / .upf).
get_project_structureList the project's RTL and constraint files.
launch_waveformOpen a VCD/FST/FSDB trace file in a waveform viewer (fire-and-forget).
lintLint a SystemVerilog/Verilog file and return structured warnings.
program_deviceProgram a bitstream to an FPGA device with openFPGALoader.
read_coverageSummarize a Verilator coverage.dat as structured line coverage.
read_rtlRead an RTL file, optionally restricted to a line range.
read_waveformRead signal values from a VCD or FST trace — no viewer needed.
run_cocotbwrite actionrun_formalwrite actionRun formal verification or equivalence checking and return structured results.
run_place_routewrite actionrun_simulationwrite actionRun RTL simulation and return structured diagnostics.
search_rtlGrep across project RTL files with surrounding context.
synthesizeSynthesize RTL and return structured utilization and timing summary.
write_rtlwrite actionWrite (or diff) proposed RTL content to a file.
Public scan report
scanner v0.1.10 · 2026-10-27 · same rubric, same numbers if you re-run it
- Code scan59 source files scanned25/25
- –Live reliabilityno gateway calls yet and no remote to proben/a
- –Tool poisoningtools not inspected (local package is not executed); not countedn/a
- Auth qualitylocal package, no credentials required12/15
- Maintenancelast push 5 days ago15/15
- Maintainer identityregistry namespace matches repository owner; GitHub account older than a year8/10
How Silica compares
Against every graded MCP server, from our own scans and uptime checks. Updated after each scan run.
- Safety score
- 92/100
- higher than 95% of 48,255 servers
- Tools
- 18
- the typical server has 7
- Tools that change things
- 28%
- typical: 0%. Fewer write tools means less an agent can break
- GitHub stars
- 13
- more than 89% of 28,688 servers
- Downloads a week
- 301
- more than 81% of 12,191 servers with a package
What its tools let an agent do: 13 read · 1 create · 4 run or deploy
Install Silica in Claude Code, Cursor or VS Code
claude mcp add silica-eda -- uvx silica-eda
What the publisher says
From the Silica repository's README, as published. We do not edit it. Read it on GitHub
<!-- mcp-name: io.github.simaanc/silica-eda -->
AI-native EDA environment · MCP server for hardware design and verification
What it does
Silica is an MCP server that gives coding agents structured access to an EDA toolchain. The agent lints, simulates, proves, synthesizes, places and routes, programs a board and reads its UART through MCP tools, and gets parsed results back (errors with file and line, timing per clock, utilization, inferred memories, counterexample traces) instead of raw logs.
That closes the loop without copy-paste: run the simulation, read the failure, fix the RTL, re-run. The server also tells the agent the order to work in and the pitfalls to avoid, and a doctor tool reports which EDA tools are installed and how to install the rest.
Silica drives tools you install yourself: open-source tools (mostly from OSS CAD Suite), and commercial ones (VCS, Questa, Xcelium, Vivado, …) when they're on PATH. How well each is tested is listed under Supported tools.
What works today
The full flow has been run end to end on a Digilent Arty A7-100T (Xilinx Artix-7) with a PicoRV32 RISC-V SoC whose firmware prints a banner, echoes UART input and drives LEDs from a timer:
- RTL and lint: Verilator, Verible and svlint, with Verilator elaborating the whole multi-file design.
- Simulation: Icarus and Verilator running the real firmware from $readmemh, with waveform (readwaveform) and line coverage (readcoverage).
- Formal: SymbiYosys prove, cover and bounded checks on the UART and FIFO, a deliberately false assertion reported as FAIL with its counterexample, and eqy equivalence.
- Synthesis: Yosys synth_xilinx, with utilization and the firmware ROM reported as block RAM with init data.
- Place and route: openXC7's nextpnr-xilinx (100 MHz target, routed at 153 MHz), and the .bit assembled with fpga-as.
- Programming: program_device (openFPGALoader) into SRAM, with the FPGA's DONE status checked.
- Serial check: capture_serial confirming the banner and the echo over the board's UART.
These runs were manual, on one machine (OSS CAD Suite 2026-10-14, openXC7 toolchain-nix 1.0.0, Verible v0.0-4296, svlint 0.9.5). CI covers the open-source tools in a weekly integration job; see Supported tools.
Known limitations
Shortened. The full README is on GitHub.
Nothing above is checked by us. What we check is on the safety report.
Silica: common questions
- Is Silica MCP server safe?
- Yes, by our scan: it is graded A (92/100). Read the Silica safety report
- How do I install Silica?
- It runs on your machine. Copy the Claude Code, Cursor, VS Code or Claude Desktop config from the install section.
- Does Silica need an API key?
- Not as far as the registry entry and our scan can tell: no credentials are declared or required.
- Is Silica maintained?
- The last commit was 13 days ago (2026-10-22). The latest release is v0.5.0.
- How does Silica compare with other MCP servers?
- safety score 92/100 (higher than 95% of 48,255 servers); tools 18 (the typical server has 7); tools that change things 28% (typical: 0%. Fewer write tools means less an agent can break). Full comparison.